;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
;  File:  memory_cfg.inc
;
;  This file is used to define g_oalAddressTable. This table is passed to
;  KernelStart to estabilish physical to virtual memory mapping. This table
;  is used also in IOMEM OAL module to map between physical and virtual
;  memory addresses via OALPAtoVA/OALVAtoPA functions.
;
;------------------------------------------------------------------------------

; Export Definition

    EXPORT  g_oalAddressTable[DATA]

;------------------------------------------------------------------------------
;
; TABLE FORMAT
;       cached address, physical address, size
;------------------------------------------------------------------------------


;g_oalAddressTable
;
;    DCD     0x80000000, 0xA0000000, 128    ; 128 MB  DDR address
;    DCD     0x88000000, 0x20000000, 1      ; ONE LEVEL SOC Reg address           
;    DCD     0x88100000, 0x30000000, 1      ; TWO LEVEL SOC Reg address
;    DCD     0x88200000, 0x30100000, 1      ; nandc address
;    DCD     0x88300000, 0x30200000, 2      ; EDC lcd Slave address
;    DCD     0x88500000, 0x30400000, 1      ; ESI S1 address
;    DCD     0x88600000, 0x30500000, 1      ; ESI S2 address
;    DCD     0x88700000, 0xFFF00000, 1      ; OnChipROM
;    DCD     0x8F000000, 0x00000000, 1      ; tcm
;    DCD     0x00000000, 0x00000000, 0      ; end of table

g_oalAddressTable                                                                       
                                                                                        
    DCD     0x80000000, 0xA0000000, 256    ; 256 MB  DDR address                        
    DCD     0x90000000, 0x20000000, 1      ; ONE LEVEL SOC Reg address                  
    DCD     0x90100000, 0x30000000, 1      ; TWO LEVEL SOC Reg address                  
    DCD     0x90200000, 0x30100000, 1      ; nandc address                              
    DCD     0x90300000, 0x30200000, 2      ; EDC lcd Slave address                      
    DCD     0x90500000, 0x30400000, 1      ; ESI S1 address                             
    DCD     0x90600000, 0x30500000, 1      ; ESI S2 address                             
    DCD     0x90700000, 0xFFF00000, 1      ; OnChipROM                                  
    DCD     0x9F000000, 0x00000000, 1      ; tcm                                        
    DCD     0x00000000, 0x00000000, 0      ; end of table          
;------------------------------------------------------------------------------
    END
